1. Field of the Invention
The present invention relates generally to testing semiconductor integrated circuit devices, and more particularly, to biasing the substrate of semiconductor integrated circuit devices comprising substrate bias voltage generating circuits.
2. Description of the Background Art
Manufacturers of semiconductor memory devices such as dynamic RAM (referred to as DRAM hereinafter) perform various tests to a completed semiconductor memory device in order to eliminate defective products. Among the various types of test, one of the most simple ones is to read and check data from all memory cells after writing "0" therein then read and check the data from all the memory cells after writing of "1" therein For example, if this test is performed for a DRAM of 4M bit, each test time T1 will be represented as the following equation (1),
T1=4.times.4.times.10.sup.6 .times.10 .mu.sec=160 sec (1)
wherein, an initial 4 corresponds to a writing of "0" , a reading of "0", writing and reading of "1". The next 4.times.10.sup.6 corresponds to a memory capacity. The last 10 .mu.sec corresponds to cycle time and a row address strobe signal RAS corresponds to a maximum pulse width. In details, the structure and operation of a conventional DRAM is referred herein to U.S. Pat. No. 3,969,706.
Actually, there are cases in which defective portions cannot be detected only with the above described test. Therefore, other tests are required in which, for example, timing of an input signal, an addressing order of address signals, a pattern of data to be written into a memory cell are changed. However, in some kinds of test, a test time is so long that the test cannot be performed. For example, in a test using a Walking Pattern known as a test approximate to the worst condition (described in Magazine of Articles of Electronic Communication Meeting 1977-12 Vol. J60-D No. 12 pp. 1031-1038), its testing time T2 is extremely long as shown in the following equation (2). ##EQU1##
Therefore, it is preferable that defective products be detected in as short a time as possible. The present invention is directed to detecting detective products in as short a time as possible.
Power supply voltage and substrate voltage of a semiconductor device are closely related to whether the device malfunctions or not under a certain condition.
FIG. 1 is a block diagram showing a general structure of a conventional substrate bias voltage generating circuit (referred to as V.sub.BB generating circuit hereinafter). In a conventional semiconductor memory device, such a V.sub.BB generating circuit is provided in order to attain a high operation speed and stability of an operation. The V.sub.BB generating circuit increases an bias of inverse direction applied to an PN junction between a P type semiconductor substrate or a P type well region and an opposite conductivity type (N type) region adjacent thereto, by supplying a fixed amount of negative voltage to the P type semiconductor substrate or the P type well region. Thereby a capacitance on the PN junction of the semiconductor memory device is decreased. As a result, the amount of signals read from the memory cell onto an internal signal line is increased, thereby obtaining high operating speed and a stable operation.
Referring to FIG. 1, a conventional V.sub.BB generating circuit is structured by a ring oscillating circuit 1 formed of a plurality of inverter circuits and a charge pump circuit 2 for receiving an output signal .phi.c of the ring oscillating circuit 1. The charge pump circuit 2 comprises a charge pumping capacitor 5 for receiving the output signal .phi.c of the ring oscillating circuit 1 at one electrode, an N type field effect transistor (referred to as n-FET hereinafter) provided between the other electrode of the charge pumping capacitor 5 and the ground, and an n-FET 4 provided between the other electrode of the charge pumping capacitor 5 and an output terminal 6. The n-FET 3 has a drain and a gate connected to the other electrode of the charge pumping capacitor 5. The n-FET 4 has a drain and a gate connected to the output terminal 6. The n-FETs 3 and 4 have a function as a rectifying element and the charge pump circuit 2 can be regarded as a kind of rectifier circuit. In such a V.sub.BB generating circuit, the charge pumping capacitor 5 is charged/discharged by a change of a potential of the output signal .phi.c of the ring oscillating circuit 1. More specifically, the substrate side, that is, the output terminal 6 side is charged to a negative potential only when a potential of the output signal .phi.c is changed from positive to negative. As the potential change continues, the substrate side is charged to a certain potential value. The value is approximately represented by the following equation (3). EQU V.sub.BB =-(V.sub.c -2V.sub.THN) (3)
In the equation (3), Vc is a voltage amplitude of the output signal .phi.c. V.sub.THN is a threshold voltage of the n-FETs 3 and 4. Vc is generally set to the same value of the power supply voltage Vcc. Therefore, the power supply voltage Vcc is applied to the ring oscillating circuit 1 through a Vcc power supply terminal 7. In this case, equation (3) will be represented as the following equation (4). EQU V.sub.BB =-(Vcc-2V.sub.THN) (4)
A V.sub.BB line A in FIG. 2 shows a relation of the above equation (4).
As described above, the power supply voltage Vcc and the substrate voltage V.sub.BB supplied by the V.sub.BB generating circuit are closely related to each other for an operation of the semiconductor memory device. For example, when the power supply voltage Vcc is large and the substrate voltage V.sub.BB is small, noise in an internal circuit is increased and a threshold voltage of a transistor in the semiconductor memory device, especially a transistor used in a memory cell is reduced, so that the semiconductor memory device is liable to malfunction. On the contrary, when the power supply voltage Vcc is small and the substrate voltage V.sub.BB is large, the amount of charge stored in the memory cell is reduced, which also causes the semiconductor memory device to malfunction. Described in more detail, in a general DRAM, there are cases where bit lines and word lines are coupled to each other due to parasitic capacitances of memory cells to drop voltages (.DELTA.V) on the bit lines (for example, refer to the second paragraph of the third column in U.S. Pat. No. 4,513,399). If a threshold voltage of a transistor in one memory cell becomes smaller than a threshold voltage V.sub.TH of transistors in other memory cells due to defects (dusts or the like) in manufacturing, the memory cell is liable to malfunction influenced by .DELTA.V. It is liable to malfunction more often when V.sub.cc is larger or .vertline.V.sub.BB .vertline. is smaller, because if .vertline.V.sub.cc .vertline. is larger, .DELTA.V becomes larger and if .vertline.V.sub.BB .vertline. is smaller, V.sub.TH of the memory transistors becomes smaller. The relation is shown as a characteristic curve B in FIG. 2. The characteristic curve B shows a result of operational characteristics of the semiconductor memory device obtained by forcibly applying the substrate voltage V.sub.BB from the external, independently of the power supply voltage Vcc. More specifically, the inside of the characteristic curve B is a normal operation region and the the outside thereof is a malfunction region. Accordingly, as long as the substrate voltage V.sub.BB is inside the characteristic curve B, the semiconductor memory device operates normally. The characteristic curve B has certain width as shown by a broken line, which indicates that operational characteristics of the semiconductor memory device are changed according to operational conditions of the semiconductor memory device (for example, a timing condition of an input signal, an addressing order of address signals, a data pattern to be written into a memory cell and the like). As described above, a semiconductor memory device is tested under various conditions. Therefore, with different kinds of tests, operational characteristics of the semiconductor memory device are changed within the width of the characteristic curve B shown by the broken lines.
In a normal semiconductor memory device, since a normal operation region is large as shown in FIG. 2, the V.sub.BB line A always exists within the normal operation region. Accordingly, the semiconductor memory device always operates normally in any kinds of tests. On the contrary, when threshold voltages of transistors of some memory cells drop extremely due to dusts produced during manufacturing and the like, operational characteristics of the semiconductor memory device are determined by the defective memory cells, so that a configuration of the characteristic curve B is changed. More specifically, the normal operation region is reduced. As a result, as shown in FIG. 3, if the V.sub.BB line A is completely outside the characteristic curve B, that is, it is in the malfunction region, the semiconductor memory device malfunctions in any kinds of tests. Accordingly, good products are easily founded.
However, the problem is that when the V.sub.BB line A is within the width of the characteristic curve B as shown in FIG. 4. More specifically, in this case, the semiconductor memory device operates normally or malfunctions depending on a kind of test. The reason is that the operational characteristics of the semiconductor memory device are changed within the width of the characteristic curve B as the operational characteristics of the semiconductor memory device differs according to a kind of test. For example, as shown in FIG. 5, if the V.sub.BB line A is located closer to the normal operation region than the characteristic curve B1 is, which is obtained in a simple short time test (for example, a test represented by the above described equation (1)), and is located closer to the malfunction region than the operational characteristic curve B2 is, which is obtained by a complicated test of a long time period (for example, a test represented by the above described equation (2)), defective products cannot be found in a simple short time test. As a result, in order to eliminate the defective products, a complicated test should be performed for a long time period, which makes a test time longer.
The present invention is directed to solve the above described problems, and its object is to provide a semiconductor integrated circuit device of which defective products can be eliminated in a simple short time test.
The semiconductor integrated circuit device according to the present invention comprises substrate voltage generating means for generating a voltage to be applied to a semiconductor substrate and wherein a value of the generated voltage is changed in response to a switching of a normal mode to a test mode.
In the present invention, the V.sub.BB line is shifted by switching a voltage of the semiconductor substrate in a test mode, thereby causing a semiconductor integrated circuit device having defective characteristics to malfunction even in a simple short time test, so that defective products are easily detected.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings,